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PCA9517
Level translating I2C-bus repeater
Rev. 03 -- 30 January 2007 Product data sheet
1. General description
The PCA9517 is a CMOS integrated circuit that provides level shifting between low voltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications. While retaining all the operating modes and features of the I2C-bus system during the level shifts, it also permits extension of the I2C-bus by providing bidirectional buffering for both the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Using the PCA9517 enables the system designer to isolate two halves of a bus for both voltage and capacitance. The SDA and SCL pins are over voltage tolerant and are high-impedance when the PCA9517 is unpowered. The 2.7 V to 5.5 V bus B-side drivers behave much like the drivers on the PCA9515A device, while the adjustable voltage bus A-side drivers drive more current and eliminate the static offset voltage. This results in a LOW on the B-side translating into a nearly 0 V LOW on the A-side which accommodates smaller voltage swings of lower voltage logic. The static offset design of the B-side PCA9517 I/O drivers prevent them from being connected to another device that has rise time accelerator including the PCA9510, PCA9511, PCA9512, PCA9513, PCA9514, PCA9515A, PCA9516A, PCA9517 (B-side), or PCA9518. The A-side of two or more PCA9517s can be connected together, however, to allow a star topography with the A-side on the common bus, and the A-side can be connected directly to any other buffer with static or dynamic offset voltage. Multiple PCA9517s can be connected in series, A-side to B-side, with no build-up in offset voltage with only time of flight delays to consider. The PCA9517 drivers are not enabled unless VCCA is above 0.8 V and VCC is above 2.5 V. The EN pin can also be used to turn the drivers on and off under system control. Caution should be observed to only change the state of the enable pin when the bus is idle. The output pull-down on the B-side internal buffer LOW is set for approximately 0.5 V, while the input threshold of the internal buffer is set about 70 mV lower (0.43 V). When the B-side I/O is driven LOW internally, the LOW is not recognized as a LOW by the input. This prevents a lock-up condition from occurring. The output pull-down on the A-side drives a hard LOW and the input level is set at 0.3VCCA to accommodate the need for a lower LOW level in systems where the low voltage side supply voltage is as low as 0.9 V.
2. Features
I 2 channel, bidirectional buffer isolates capacitance and allows 400 pF on either side of the device I Voltage level translation from 0.9 V to 5.5 V and from 2.7 V to 5.5 V I Footprint and functional replacement for PCA9515/15A I I2C-bus and SMBus compatible
NXP Semiconductors
PCA9517
Level translating I2C-bus repeater
I I I I I I I I I I
Active HIGH repeater enable input Open-drain input/outputs Lock-up free operation Supports arbitration and clock stretching across the repeater Accommodates Standard mode and Fast mode I2C-bus devices and multiple masters Powered-off high-impedance I2C-bus pins A-side operating supply voltage range of 0.9 V to 5.5 V B-side operating supply voltage range of 2.7 V to 5.5 V 5 V tolerant I2C-bus and enable pins 0 Hz to 400 kHz clock frequency (the maximum system operating frequency may be less than 400 kHz because of the delays added by the repeater). I ESD protection exceeds 2000 V HBM per JESD22-A114, 150 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101 I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Packages offered: SO8 and TSSOP8
3. Ordering information
Table 1. Ordering information Tamb = -40 C to +85 C Type number PCA9517D PCA9517DP
[1]
Topside mark
Package Name TSSOP8[1] Description plastic small outline package; 8 leads; body width 3.9 mm plastic thin shrink small outline package; 8 leads; body width 3 mm Version SOT96-1 SOT505-1
PCA9517 SO8 9517
Also known as MSOP8
4. Functional diagram
VCCA VCCB
PCA9517
SDAA SDAB
SCLA VCCB pull-up resistor EN
002aac200
SCLB
GND
Fig 1. Functional diagram of PCA9517
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
5. Pinning information
5.1 Pinning
VCCA SCLA SDAA GND
1 2
8 7
VCCB SCLB SDAB EN
VCCA SCLA SDAA GND
1 2 3 4
002aac199
8 7
VCCB SCLB SDAB EN
PCA9517D
3 4
002aac198
6 5
PCA9517DP
6 5
Fig 2. Pin configuration for SO8
Fig 3. Pin configuration for TSSOP8 (MSOP8)
5.2 Pin description
Table 2. Symbol VCCA SCLA SDAA GND EN SDAB SCLB VCCB Pin description Pin 1 2 3 4 5 6 7 8 Description A-side supply voltage (0.9 V to 5.5 V) serial clock A-side bus serial data A-side bus supply ground (0 V) active HIGH repeater enable input serial data B-side bus serial clock B-side bus B-side supply voltage (2.7 V to 5.5 V)
6. Functional description
Refer to Figure 1 "Functional diagram of PCA9517". The PCA9517 enables I2C-bus or SMBus translation down to VCCA as low as 0.9 V without degradation of system performance. The PCA9517 contains two bidirectional open-drain buffers specifically designed to support up-translation/down-translation between the low voltage (as low as 0.9 V) and a 3.3 V or 5 V I2C-bus or SMBus. All inputs and I/Os are overvoltage tolerant to 5.5 V even when the device is unpowered (VCCB and/or VCCA = 0 V). The PCA9517 includes a power-up circuit that keeps the output drivers turned off until VCCB is above 2.5 V and the VCCA is above 0.8 V. VCCB and VCCA can be applied in any sequence at power-up. After power-up and with the enable (EN) HIGH, a LOW level on the A-side (below 0.3VCCA) turns the corresponding B-side driver (either SDA or SCL) on and drives the B-side down to about 0.5 V. When the A-side rises above 0.3VCCA the B-side pull-down driver is turned off and the external pull-up resistor pulls the pin HIGH. When the B-side falls first and goes below 0.3VCCB the A-side driver is turned on and the A-side pulls down to 0 V. The B-side pull-down is not enabled unless the B-side voltage goes below 0.4 V. If the B-side low voltage does not go below 0.5 V, the A-side driver will turn off when the B-side voltage is above 0.7VCCB. If the B-side low voltage goes below 0.4 V, the B-side pull-down driver is enabled and the B-side will only
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
be able to rise to 0.5 V until the A-side rises above 0.3VCCA, then the B-side will continue to rise being pulled up by the external pull-up resistor. The VCCA is only used to provide the 0.3VCCA reference to the A-side input comparators and for the power good detect circuit. The PCA9517 logic and all I/Os are powered by the VCCB pin.
6.1 Enable
The EN pin is active HIGH with an internal pull-up to VCCB and allows the user to select when the repeater is active. This can be used to isolate a badly behaved slave on power-up until after the system power-up reset. It should never change state during an I2C-bus operation because disabling during a bus operation will hang the bus and enabling part way through a bus cycle could confuse the I2C-bus parts being enabled. The enable pin should only change state when the global bus and the repeater port are in an idle state to prevent system failures.
6.2 I2C-bus systems
As with the standard I2C-bus system, pull-up resistors are required to provide the logic HIGH levels on the buffered bus (standard open-collector configuration of the I2C-bus). The size of these pull-up resistors depends on the system, but each side of the repeater must have a pull-up resistor. This part designed to work with Standard mode and Fast mode I2C-bus devices in addition to SMBus devices. Standard mode I2C-bus devices only specify 3 mA output drive; this limits the termination current to 3 mA in a generic I2C-bus system where Standard mode devices and multiple masters are possible. Under certain conditions higher termination currents can be used. Please see Application Note AN255, I2C/SMBus Repeaters, Hubs and Expanders for additional information on sizing resistors and precautions when using more than one PCA9517 in a system or using the PCA9517 in conjunction with other bus buffers.
PCA9517_3
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Product data sheet
Rev. 03 -- 30 January 2007
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PCA9517
Level translating I2C-bus repeater
7. Application design-in information
A typical application is shown in Figure 4. In this example, the system master is running on a 3.3 V I2C-bus while the slave is connected to a 1.2 V bus. Both buses run at 400 kHz. Master devices can be placed on either bus.
3.3 V
1.2 V
10 k
10 k
10 k
10 k
VCCB SDA SCL BUS MASTER 400 kHz EN bus B SDAB SCLB
VCCA SDAA SCLA SDA SCL
PCA9517
SLAVE 400 kHz
bus A
002aac201
Fig 4. Typical application
The PCA9517 is 5 V tolerant, so it does not require any additional circuitry to translate between 0.9 V to 5.5 V bus voltages and 2.7 V to 5.5 V bus voltages. When the A-side of the PCA9517 is pulled LOW by a driver on the I2C-bus, a comparator detects the falling edge when it goes below 0.3VCCA and causes the internal driver on the B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the PCA9517 falls, first a CMOS hysteresis type input detects the falling edge and causes the internal driver on the A-side to turn on and pull the A-side pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 8 and Figure 9. If the bus master in Figure 4 were to write to the slave through the PCA9517, waveforms shown in Figure 8 would be observed on the A bus. This looks like a normal I2C-bus transmission except that the HIGH level may be as low as 0.9 V, and the turn on and turn off of the acknowledge signals are slightly delayed. On the B bus side of the PCA9517, the clock and data lines would have a positive offset from ground equal to the VOL of the PCA9517. After the 8th clock pulse, the data line will be pulled to the VOL of the slave device which is very close to ground in this example. At the end of the acknowledge, the level rises only to the LOW level set by the driver in the PCA9517 for a short delay while the A bus side rises above 0.3VCCA then it continues HIGH. It is important to note that any arbitration or clock stretching events require that the LOW level on the B bus side at the input of the PCA9517 (VIL) be at or below 0.4 V to be recognized by the PCA9517 and then transmitted to the A bus side. Multiple PCA9517 A-sides can be connected in a star configuration (Figure 5), allowing all nodes to communicate with each other. Multiple PCA9517s can be connected in series (Figure 6) as long as the A-side is connected to the B-side. I2C-bus slave devices can be connected to any of the bus segments. The number of devices that can be connected in series is limited by repeater delay/time-of-flight considerations on the maximum bus speed requirements.
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
VCCA
VCCB
10 k
10 k
10 k
10 k
VCCA SDA SCL BUS MASTER EN SDAA SCLA
VCCB SDAB SCLB SDA SCL
PCA9517
SLAVE 400 kHz
10 k
10 k
VCCA SDAA SCLA
VCCB SDAB SCLB SDA SCL
PCA9517
EN
SLAVE 400 kHz
10 k
10 k
VCCA SDAA SCLA
VCCB SDAB SCLB SDA SCL
PCA9517
EN
SLAVE 400 kHz
002aac202
Fig 5. Typical star application
VCC
10 k
10 k
10 k
10 k
10 k
10 k
10 k
10 k
SDA SCL BUS MASTER
SDAA SCLA
SDAB SCLB
SDAA SCLA
SDAB SCLB
SDAA SCLA
SDAB SCLB
SDA SCL
PCA9517
EN
PCA9517
EN
PCA9517
EN
SLAVE 400 kHz
002aac203
Fig 6. Typical series application
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PCA9517
Level translating I2C-bus repeater
CARD 1 VCCA VCCB
CARD 2
RPU
RPU
10 k
10 k
10 k (optional)
VCCA
75
VCCB SDAB SCLB EN GND MASTER OR SLAVE
75
SDAA SCLA
002aac637
Fig 7. Typical application of PCA9517 driving a short cable
9th clock pulse acknowledge SCL
SDA
002aac775
Fig 8. Bus A (0.9 V to 5.5 V bus) waveform
9th clock pulse acknowledge SCL
SDA VOL of PCA9517
002aac205
VOL of slave
Fig 9. Bus B (2.7 V to 5.5 V) waveform
PCA9517_3
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
8. Limiting values
Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCCB VCCA Vbus I Ptot Tstg Tamb Tj Parameter supply voltage, B-side bus supply voltage, A-side bus voltage on I2C-bus B-side, or enable (EN) DC current total power dissipation storage temperature ambient temperature junction temperature operating in free air any pin Conditions 2.7 V to 5.5 V adjustable Min -0.5 -0.5 -0.5 -55 -40 Max +7 +7 +7 50 100 +125 +85 +125 Unit V V V mA mW C C C
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
9. Static characteristics
Table 4. Static characteristics VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VCCB VCCA ICC(VCCA) ICCH supply voltage, B-side bus supply voltage, A-side bus supply current on pin VCCA HIGH-state supply current both channels HIGH; VCC = 5.5 V; SDAn = SCLn = VCC both channels LOW; VCC = 5.5 V; one SDA and one SCL = GND; other SDA and SCL open VCC = 5.5 V; SDAn = SCLn = VCC
[1]
Parameter
Conditions
Min 2.7 0.9 -
Typ 1.5
Max 5.5 5.5 1 5
Unit V V mA mA
ICCL
LOW-state supply current
-
1.5
5
mA
ICCAc
quiescent supply current in contention HIGH-level input voltage LOW-level input voltage LOW-level input voltage contention input clamping voltage input leakage current LOW-level input current LOW-level output voltage LOW-level input voltage below output LOW-level voltage HIGH-level output leakage current input/output capacitance
-
1.5
5
mA
Input and output SDAB and SCLB VIH VIL VILc VIK ILI IIL VOL VOL-VILc ILOH Cio 0.7VCCB
[2]
0.4 0.52 6 6 0.1 6 6
5.5 +0.3VCCB -1.2 1 10 0.6 70 10 7 7 5.5 +0.3VCCA -1.2 1 10 0.2 10 7 7
V V V V A A V mV A pF pF V V V A A V A pF pF
-0.5 -0.5 0.47 0.7VCCA
II = -18 mA VI = 3.6 V SDA, SCL; VI = 0.2 V IOL = 100 A or 6 mA guaranteed by design VO = 3.6 V VI = 3 V or 0 V; VCC = 3.3 V VI = 3 V or 0 V; VCC = 0 V
Input and output SDAA and SCLA VIH VIL VIK ILI IIL VOL ILOH Cio HIGH-level input voltage LOW-level input voltage input clamping voltage input leakage current LOW-level input current LOW-level output voltage HIGH-level output leakage current input/output capacitance II = -18 mA VI = 3.6 V SDA, SCL; VI = 0.2 V IOL = 6 mA VO = 3.6 V VI = 3 V or 0 V; VCC = 3.3 V VI = 3 V or 0 V; VCC = 0 V
[3]
-0.5 -
PCA9517_3
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
Table 4. Static characteristics ...continued VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Enable VIL VIH IIL(EN) ILI Ci
[1] [2] [3]
Parameter LOW-level input voltage HIGH-level input voltage LOW-level input current on pin EN input leakage current input capacitance
Conditions
Min -0.5 0.7VCCB
Typ -10 6
Max +0.3VCCB 5.5 -30 +1 7
Unit V V A A pF
VI = 0.2 V, EN; VCC = 3.6 V VI = 3.0 V or 0 V
-1 -
LOW-level supply voltage. VIL specification is for the first LOW level seen by the SDAB/SCLB lines. VILc is for the second and subsequent LOW levels seen by the SDAB/SCLB lines. VIL for A-side with envelope noise must be below 0.3VCCA for stable performance.
10. Dynamic characteristics
Table 5. Dynamic characteristics VCC = 2.7 V to 5.5 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified.[1][2] Symbol tPLH tPHL Parameter LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay Conditions B-side to A-side; Figure 12 B-side to A-side; Figure 10 VCCA 2.7 V VCCA 3 V tt(LH) tt(HL) LOW-to-HIGH transition time HIGH-to-LOW transition time A-side; Figure 10 A-side; Figure 10 VCCA 2.7 V VCCA 3 V tPLH tPHL tt(LH) tt(HL) tsu th
[1]
[5] [5] [4]
Min 100 30 10 10 1 20
[6] [6]
Typ[3] 170 80 66 20 77 70 53 79 140 48 -
Max 250 110 300 30 105 175 110 230 170 90 -
Unit ns ns ns ns ns ns ns ns ns ns ns ns
LOW-to-HIGH propagation delay HIGH-to-LOW propagation delay LOW-to-HIGH transition time HIGH-to-LOW transition time set-up time hold time
A-side to B-side; Figure 11 A-side to B-side; Figure 11 B-side; Figure 11 B-side; Figure 11 EN HIGH before START condition EN HIGH after STOP condition
25 60 120 30
[7] [7]
100 100
Times are specified with loads of 1.35 k pull-up resistance and 57 pF load capacitance on the B-side, and 167 pull-up resistance and 57 pF load capacitance on the A-side. Different load resistance and capacitance will alter the RC time constant, thereby changing the propagation delay and transition times. Pull-up voltages are VCCA on the A-side and VCCB on the B-side. Typical values were measured with VCCA = 3.3 V at Tamb = 25 C, unless otherwise noted. The tPLH delay data from B-side to A-side is measured at 0.5 V on the B-side to 0.5VCCA on the A-side when VCCA is less than 2 V, and 1.5 V on the A-side if VCCA is greater than 2 V. Typical value measured with VCCA = 2.7 V at Tamb = 25 C. The proportional delay data from A-side to B-side is measured at 0.3VCCA on the A-side to 1.5 V on the B-side. The enable pin, EN, should only change state when the global bus and the repeater port are in an idle state.
[2] [3] [4] [5] [6] [7]
PCA9517_3
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
10.1 AC waveforms
3.0 V input 1.5 V tPHL 80 % output 1.5 V 0.1 V tPLH 80 % 1.2 V output VOL tPHL 80 % tPLH 3.0 V 1.5 V 20 % tt(HL) 1.5 V 20 % 80 % tt(LH)
002aac208
VCCA input 0.3VCCA 0.3VCCA
0.6 V 20 % tt(HL)
0.6 V 20 %
tt(LH)
002aac207
Fig 10. Propagation delay and transition times; B-side to A-side
Fig 11. Propagation delay and transition times; A-side to B-side
input SDAB, SCLB 0.5 V
output SCLA, SDAA tPLH
50 % if VCCA is less than 2 V 1.5 V if VCCA is greater than 2 V
002aac209
Fig 12. Propagation delay
11. Test information
VCC(B) VCC(B) VCC(A) PULSE GENERATOR VI DUT
RT CL RL
VO
002aab649
RL = load resistor; 1.35 k on B-side; 167 on A-side (0.9 V to 2.7 V) and 450 on A-side (3.0 V to 5.5 V). CL = load capacitance includes jig and probe capacitance; 57 pF RT = termination resistance should be equal to Zo of pulse generators
Fig 13. Test circuit for open-drain outputs
PCA9517_3
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
12. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 14. Package outline SOT96-1 (SO8)
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm
SOT505-1
D
E
A
X
c y HE vMA
Z
8
5
A2 pin 1 index
A1
(A3)
A
Lp L
1
e bp
4
detail X wM
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.45 0.25 c 0.28 0.15 D(1) 3.1 2.9 E(2) 3.1 2.9 e 0.65 HE 5.1 4.7 L 0.94 Lp 0.7 0.4 v 0.1 w 0.1 y 0.1 Z(1) 0.70 0.35 6 0
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT505-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-04-09 03-02-18
Fig 15. Package outline SOT505-1 (TSSOP8)
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Product data sheet
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PCA9517
Level translating I2C-bus repeater
13. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus PbSn soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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PCA9517
Level translating I2C-bus repeater
13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 16) than a PbSn process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 6 and 7
Table 6. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 7. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 16.
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Level translating I2C-bus repeater
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 16. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Abbreviations
Table 8. Acronym CDM CMOS ESD HBM I2C-bus MM SMBus Abbreviations Description Charged Device Model Complementary Metal Oxide Silicon ElectroStatic Discharge Human Body Model Inter Integrated Circuit bus Machine Model System Management Bus
PCA9517_3
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 -- 30 January 2007
16 of 19
NXP Semiconductors
PCA9517
Level translating I2C-bus repeater
15. Revision history
Table 9. Revision history Release date 20070130 Data sheet status Product data sheet Change notice Supersedes PCA9517_2 Document ID PCA9517_3 Modifications:
* * * * * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Section 2 "Features", 15th bullet item: changed "200 V MM per JESD22-A115" to "150 V MM per JESD22-A115" Table 4 "Static characteristics" added new Table note 3, and its reference in sub-section "Input and output SDAA and SCLA", symbol VIL. added (new) Figure 7 "Typical application of PCA9517 driving a short cable" Figure 8 "Bus A (0.9 V to 5.5 V bus) waveform": SDA signal modified Figure 9 "Bus B (2.7 V to 5.5 V) waveform": SDA signal modified Table 5 "Dynamic characteristics": - tt(LH), A-side: changed reference to timing diagram from Figure 11 to Figure 10 - tt(HL), A-side: changed reference to timing diagram from Figure 11 to Figure 10 - tt(LH), B-side: changed reference to timing diagram from Figure 10 to Figure 11 - tt(HL), B-side: changed reference to timing diagram from Figure 10 to Figure 11
PCA9517_2 (9397 750 14918) PCA9517_1 (9397 750 13252)
20060615 20041005
Product data sheet Product data sheet
-
PCA9517_1 -
PCA9517_3
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 -- 30 January 2007
17 of 19
NXP Semiconductors
PCA9517
Level translating I2C-bus repeater
16. Legal information
16.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
16.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
17. Contact information
For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com
PCA9517_3
(c) NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 03 -- 30 January 2007
18 of 19
NXP Semiconductors
PCA9517
Level translating I2C-bus repeater
18. Contents
1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 10.1 11 12 13 13.1 13.2 13.3 13.4 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 I2C-bus systems . . . . . . . . . . . . . . . . . . . . . . . . 4 Application design-in information . . . . . . . . . . 5 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 8 Static characteristics. . . . . . . . . . . . . . . . . . . . . 9 Dynamic characteristics . . . . . . . . . . . . . . . . . 10 AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 11 Test information . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Introduction to soldering . . . . . . . . . . . . . . . . . 14 Wave and reflow soldering . . . . . . . . . . . . . . . 14 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 14 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 17 Legal information. . . . . . . . . . . . . . . . . . . . . . . 18 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 18 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Contact information. . . . . . . . . . . . . . . . . . . . . 18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 30 January 2007 Document identifier: PCA9517_3

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